1. Field of the Invention
The present invention relates to a digital frequency converter for converting the frequency of a signal using digital signal processing.
2. Description of the Related Art
EER (Envelope Elimination and Restoration) is one of many conventional signal processing schemes used to improve efficiency and reduce power consumption in processing a linearly modulated signal, such as a single-side-band (SSB) modulated signal, for transmission (e.g., referring to the specification of U.S. Pat. No. 4,176,319). The EER scheme converts a linearly modulated signal into phase information and amplitude information of polar coordinates. The phase amplitude information is processed independently. Resulting distortion is small, so the EER scheme is considered an effective transmission scheme with excellent efficiency. However, in analog signal processing by EER, a large error may occur when a linearly modulated signal is converted into a polar coordinate signal. It is impossible to achieve good power efficiency in combining the phase information and the amplitude information, so it is difficult to put the EER scheme to practical use.
Recently, however, with the development of digital signal processing techniques, a digital signal can be processed at high speeds, so that conversion of a linearly modulated signal into a polar coordinate signal occurs with only a small error. Further, amplifiers, such as class D, class E, and class F amplifiers, have excellent power efficiency, making it possible to put the EER scheme with a low distortion characteristic and a high power efficiency characteristic to practical use (e.g., referring to the specification of U.S. Pat. No. 5,705,959).
Under the EER scheme, a polar coordinate signal converted from a band-limited orthogonal coordinate signal has a relatively wider band, so a high sampling frequency is necessary to prevent aliasing from occurring in the converted polar coordinate signal. To this end, a method of obtaining a high sampling frequency was developed that involves performing interpolation of an orthogonal coordinate signal before it is converted into a polar coordinate signal (e.g., referring to the specification of U.S. Pat. No. 4,972,440).
In addition, frequency conversion may be executed by processing analog signals in a phase modulator as disclosed in U.S. Pat. No. 4,972,440. Frequency conversion may also be executed using complex processing by digital signal processing as shown in FIG. 9. To be specific, FIG. 9 is a block diagram illustrating a digital frequency converter for executing frequency conversion using complex processing by digital signal processing. Modulation signals MOD_I and MOD_Q are inputted to a phase detector 52 through a filter 51. Phase information is extracted from the MOD_I and MOD_Q by the phase detector 52. Then, a numeral control oscillator (NCO) 53 is controlled by the extracted phase information, thereby generating a polar coordinate phase modulation signal.
Then, Np-time upsampling is executed by an interpolator 54. Frequency conversion is executed in a complex mixer 56 by a signal outputted from an NCO 55 as a function of a desired frequency. The resulting orthogonal coordinate phase modulation signals Phase_I and Phase_Q are output from the NCO 55. In addition, the modulation signals MOD_I and MOD_Q are input to an amplitude detector 57 through the filter 51. Amplitude information Amp is extracted and output from the modulation signals MOD_I and MOD_Q by the amplitude detector 57.
However, when the sampling frequency of a signal increases to the sampling frequency of a D/A converter by interpolation as described in U.S. Pat. No. 4,972,440, power consumption increases according to the variation of a polar coordinate signal. To be specific, according to the technique described in U.S. Pat. No. 4,972,440, although the conversion of amplitude information and phase information is executed using a ROM (Read Only Memory), the increase of power consumption with high-speed sampling frequency processing is a problem that cannot be disregarded. In addition, when the phase information is outputted as a high IF (Intermediate Frequency) or RF (Radio Frequency), a higher sampling frequency is required, so power consumption significantly increases, creating a problem.
Also, when the frequency conversion is executed using complex processing by the digital signal processing as shown in FIG. 9, four multipliers are necessary to execute multiplication of a real-axis signal by a real-axis signal, an imaginary-axis signal by an imaginary-axis signal, a real-axis signal by an imaginary-axis signal, and an imaginary-axis signal by a real-axis signal. In addition, an adder or a subtractor is necessary to sum output values of the multipliers increasing circuit size and power consumption. Furthermore, the high power efficiency of the EER scheme deteriorates.